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rev. 2.3 january 2009 www.aosmd.com page 1 of 14 aoz8005 ultra-low capacitanc e tvs diode array general description the aoz8005 is a transient voltage suppressor array designed to protect high speed data lines such as hdmi and gigabit ethernet from damaging esd events. this device incorporates eight surge rated, low capaci- tance steering diodes and a tvs in a single package. during transient conditions, t he steering diodes direct the transient to either the positive side of the power supply line or to ground. the aoz8005 provides a typical line to line capacitance of 0.47pf and low insertion loss up to 2ghz providing greater signal integrity maki ng it ideally suited for hdmi 1.3 applications, such as digital tvs, dvd players, set-top boxes and mobile computing devices. the aoz8005 comes in rohs compliant, tiny sot-23-6 and msop-10 packages and is rated -40c to +85c junction temperature range. the msop package features a flow through layout design. features esd protection for high-speed data lines: ? iec 61000-4-2, level 4 (esd) immunity test ? 15kv (air discharge) and 8kv (contact discharge) ? human body model (hbm) 15kv array of surge rated diodes with internal tvs diode small package saves board space protects four i/o lines low capacitance between i/o lines: 0.47pf low clamping voltage low operating voltage: 5.0v applications hdmi ports monitors and flat panel displays set-top box usb 2.0 power and data line protection video graphics cards digital video interface (dvi) 10/100/1000 ethernet notebook computers typical application figure 1. hdmi ports aoz8005 aoz8005 tx2+ tx2- tx1+ tx1- tx0+ tx0- clk+ clk- hdmi transmitter rx2+ rx2- rx1+ rx1- rx0+ rx0- clk+ clk- hdmi receiver connector connector aoz8005 aoz8005
rev. 2.3 january 2009 www.aosmd.com page 2 of 14 aoz8005 ordering information all aos products are offered in packages with pb -free plating and compliant to rohs standards. parts marked as green products (with ?l? suffix) use reduc ed levels of halogens, and are also rohs compliant. please visit www.aosmd.com/web/qualit y/rohs_compliant.jsp for additional information. pin configuration absolute maximum ratings exceeding the absolute maximum ratings may damage the device. notes: 1. iec 61000-4-2 discharge with c discharge = 150pf, r discharge = 330 ? . 2. human body discharge per mil-std-883, method 3015 c discharge = 100pf, r discharge = 1.5k ? . maximum operating ratings part number ambient temperature range package environmental aoz8005ci -40c to +85c sot-23-6 rohs compliant green product aoz8005cil sot-23-6 AOZ8005FI msop-10 1 2 3 6 5 4 ch1 vn ch2 ch4 vp ch3 sot23-6 (top view) 1 2 3 4 5 10 9 8 7 6 ch1 ch2 vn ch3 ch4 nc nc vp nc nc msop-10 (top view) parameter rating storage temperature (t s ) -65c to +150c esd rating per iec61000-4-2, contact (1) 8kv esd rating per iec61000-4-2, air (1) 15kv esd rating per human body model (2) 15kv parameter rating junction temperature (t j ) -40c to +125c
rev. 2.3 january 2009 www.aosmd.com page 3 of 14 aoz8005 electrical characteristics t a = 25c unless otherwise specified. specifications in bold indicate a temperature range of -40c to +85c. notes: 3. the working peak reverse voltage, v rwm , should be equal to or greater than the dc or continuous peak operating voltage level. 4. v br is measured at the pulse test current i t . 5. measurements performed using a 100ns transmission line pulse (tlp) system. 6. measure performed with no external capacitor on v p . symbol parameter conditions min. typ. max. units v rwm reverse working voltage between vp and vn (3) 5.5 v v br reverse breakdown volt- age i t = 1ma, between vp and vn (4) 6.6 v i r reverse leakage current v rwm = 5v, between vp and vn 1 a v f diode forward voltage i f = 15ma 0.70 0.85 1 v v cl channel clamp voltage positive transients negative transient i pp = 1a, tp = 100ns, any i/o pin to ground (5) 10.50 -2.00 v v channel clamp voltage positive transients negative transient i pp = 5a, tp = 100ns, any i/o pin to ground (5) 12.50 -3.50 v v channel clamp voltage positive transients negative transient i pp = 12a, tp = 100ns, any i/o pin to ground (5) 16.00 -5.50 v v c j channel input capacitance v r = 0v, f = 1mhz, any i/o pin to ground (6) 1.0 1.05 pf v r = 0v, f = 1mhz, between i/o pins (6) 0.47 0.50 pf v p = 3.3v, v r = 1.65v, f = 1mhz, any i/o pin to ground 0.75 0.85 pf v p = 5.0v, v r = 2.5v, f = 1mhz, any i/o pins to ground 0.75 0.85 pf c j channel input capacitance matching v r = 0v, f = 1mhz, between i/o pins 0.03 pf
rev. 2.3 january 2009 www.aosmd.com page 4 of 14 aoz8005 typical operating characteristics clamping voltage vs. peak pulse current (tperiod = 100ns, tr = 1ns) 024681012 peak pulse current (a) clamping voltage, vcl (v) forward voltage vs. forward current (tperiod = 100ns, tr = 1ns) 7 6 5 4 3 2 1 0 forward current (a) forward voltage (v) i/o ? gnd insertion loss vs. frequency frequency (mhz) insertion loss (db) 1 100 10 1000 024681012 capacitance vs. reverse voltage 1.5 1 0.5 0 21 18 15 12 9 6 3 0 -3 -6 -9 -12 -15 -18 -21 01 vp = floating vp = 3.3v 2345 reverse volts, vr (v) capacitance (pf) 17 16 15 14 13 12 11 10 0.5 1.5 2.5 3.5 4.5 vp = floating vp = 3.3v insertion loss vs. frequency frequency (mhz) s21 (db) 10 100 1,000 10,000 1 3 0 -3 -6 -9 -12 vp = floating -3db 2,340mhz esd response (8kv contact per iec61000-4-2)
rev. 2.3 january 2009 www.aosmd.com page 5 of 14 aoz8005 application information the aoz8005 tvs is design to protect four high speed data lines from esd and transient over-voltage by clamping them to a fixed voltage. when the voltages on the protected lines exceed the limit, the internal steering diode are forward bias will co nduct the harmful transient away from the sensitive circuitry. as system frequency increase, printed circuit board layout becomes more complex. a successful high speed board must integrate the device and traces while avoiding signal transmission problems associated with hdmi data speed. high speed hdmi pcb layout guidelines printed circuit board layout is the key to achieving the highest level of surge immunity on power and data lines. the location of the protection devices on the pcb is the simplest and most important design rule to follow. the aoz8005 devices should be lo cated as close as possible to the noise source. the placement of the aoz8005 devices should be used on all data and power lines that enter or exit the pcb at th e i/o connector. in most systems, surge pulses occur on data and power lines that enter the pcb through the i/o connector. placing the aoz8005 devices as close as possible to the noise source ensures that a sur ge voltage will be clamped before the pulse can be coupled into adjacent pcb traces. in addition, the pcb should use the shortest possible traces. a short trace length equates to low impedance, which ensures t hat the surge energy will be dissipated by the aoz8005 device. long signal traces will act as antennas to receive energy from fields that are produced by the esd pulse. by keeping line lengths as short as possible, the efficien cy of the line to act as an antenna for esd related fields is reduced. minimize inter- connecting line lengths by placing devices with the most interconnect as close together as possible. the protec- tion circuits should shunt t he surge voltage to either the reference or chassis ground. shunting the surge voltage directly to the ic?s signal ground can cause ground bounce. the clamping performance of tvs diodes on a single ground pcb can be improved by minimizing the impedance with relatively short and wide ground traces. the pcb layout and ic pack age parasitic inductances can cause significant overshoot to the tvs?s clamping voltage. the inductance of the pcb can be reduced by using short trace lengths and multiple layers with sepa- rate ground and power planes. one effective method to minimize loop problems is to incorporate a ground plane in the pcb design. the aoz8005 ultra-low capacitance tvs is designed to protect four high speed data transmission lines from transient over-voltages by clam ping them to a fixed refer- ence. the low inductance and construction minimizes voltage overshoot during high current surges. when the voltage on the protected line exceeds the reference voltage the internal steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. the aoz8005 is designed for the ease of pcb layout by allowing the traces to run underneath the device. the pinout of the ao z8005 is design to simply drop onto the io lines of a high definition multimedia interface (hdmi) design without having to divert the signal lines that may add more parasitic inductance. pins 1, 2, 4 and 5 are connected to the internal tvs devices and pins 6, 7, 9 and 10 are no connects. the no connects was done so the package can be securely soldered onto the pcb surface. see figure 2. figure 2. flow through layout for two line pair it is crucial that the layo ut is successful for a hdmi design pcb board. some of the problems associated with high speed design are matching impedance of the traces and to minimize the crosstalk between parallel traces. this application note is to provide you as much information to successfully design a high speed pcb using alpha & omega devices. the hdmi video signals are transmitted on a very high speed pair of traces and any amount of capacitance, inductance or even bends in a trace can cause the impedance of a differential pair to drop as much as 40 ? . this is not desirable because hdmi ports must maintain a 100 ? 15% on each of the four pairs of its differential lines per hdmi compliance te st specifications. the hdmi cts specifies that the impedance on the differen- tial pair of a receiver must be measured using a time domain reflectometry method with a pulse rise time of 200ps. the tdr measurements of the pcb traces allows to locate and model discontinuities cause by the geometrical features of a bend and by the frequency- dependant losses of the trace itself. these fast edge rates can contribute to noise and crosstalk, depending on the traces and pcb dielectric construction material. ch 1 ch 2 vp ch 3 ch 4 ch 1 ch 2 vn ch 3 ch 4
rev. 2.3 january 2009 www.aosmd.com page 6 of 14 aoz8005 material selection is another aspect that determines good characteristic impedance in the lines. different material will give you different results. the dielectric material will have the dielectric constant ( r ). where q 1 , q 2 = charges, r = distance between charges (m), f = force(n), = permittivity of dielectric (f/m). each pcb substrate has a different relative dielectric constant. the dielectric consta nt is the permittivity of a relative that of empty space. where r = dielectric constant, = permittivity, and o = permittivity of empty space. the dielectric constant affects the impedance of a trans- mission line and can propagate faster in materials that have a lower r . the frequency in your design will depend on the material being used. with equation 1 you can determine the type of material to use. if higher fre- quency is required other board material maybe consid- ered. getek is another material that can be used in high speed boards. they have a typical r between 3.6 to 4.0. the most common type of dielectric material used for pcb is fr-4. typical dielectr ic constant for fr-4 is between 4.0 to 4.5. most pc b manufacture will be able to give you the exact value of th e fr-4 dielectric constant. once you determined the dielectric constant of the board material you can start to calc ulate the impedance of each trace. below are the formulas fo r a microstrip layout. this impedance is dependant on the width of the microstrip (w) the thickness (t) of the trace and the height (h) of the fr4 material, and (d) trace edge to edge spacing. figure 3. typical value of w = 12.6 m il, h = 10mils, d = 10mils, t = 1.4mils and r = 4.0 with the equation below for a microstrip impedance yields: by solving for zo you can calculate the differential impedance with the equation below. adjust the trace width, height, distance between the traces and fr4 thickness to obtain the desired 100 ? differential impedance. the general rule of thumb is to route the traces as short as possible, use differential routing strategies whenever feasible and match the length and bends to each of the differential traces. the graphs below show the differential impedance with varying trace width without the aoz8005 msop-10 package part on it. each of the graphs and board layout represent changing trace width from 50 ? to 80 ? in increment of 10 ? . figure 4. 100 ? differentia l impedance max 103 ? , min 97 ? figure 5. 120 ? differentia l impedance max 110 ? , min 102 ? f q 1 q 2 4 r 2 --------------- = (1) r o ----- = (2) trace wd dielectric material t h w ground r zo 87 r 1.41 + -------------------------- 5.98 h 0.8 wt + --------------------- - ?? ?? ln == (3) zo 61.73 = zdiff 2 zo 10.48 e 0.96 d h --- - ? ? ?? ?? ?? = (4) zdiff 100.77 =
rev. 2.3 january 2009 www.aosmd.com page 7 of 14 aoz8005 figure 6. 140 ? differential impedance max 102 ? , min 92 ? figure 7. 160 ? differential impedance max 123 ? , min 109 ? figure 8. differential impedance by adding a tvs onto the traces it can have a large effect on the impedance of the line. this addition of a capacitance added to a 100 ? differential transmission line without any compensation may decrease the impedance as much as 20 ? or more. below is a formula to calculate the length for the compensation of c (tvs) . figure 7. z 0 is the normal 61 ? differential impedance on the trace. z 1 is the needed impedance to compensate for the added c (tvs) k is defined as the unloaded impedance of the adjusted trace. x is the length of the trace needed for the compensation. is the propagation delay time required for a signal to travel from one point to another. this value should be less than 200ps. from the above method the designer should layout the boards with a 50 ? common mode trace. the result should give you approximately 100 ? differential imped- ance. z 1 is the impedance that you choose in order to compensate the tvs capacitance. based on z 1 value, we can get the length of the segment from the above equations. with the value of z 1 = 80 ? , zo = 61 ? , c (tvs) = 0.94 and = 180. the x(mils) equates to 580 mils. page 8 has a series of gra ph that represent changing width and length of the trace from 50 ? to 80 ? in increment of 10 ? with a msop-10 package solder onto the board. as you can observe from the graphs, a small incremental capacitance that is added to the differential lines can significantly decrease the differential imped- ance. thus violated the hdmi specification of 100 ? 15%. 140 120 100 80 60 40 20 0 50 55 60 65 70 75 80 common mode impedance ( ) differentail impedance ( ) max. min. x zo = 61 zo = 61 z 1 c (tvs) k z 1 z 0 ------ = (5) x z 0 c tvs --------------------- ?? ?? k k 2 1 ? --------------- - ?? ?? = (6)
rev. 2.3 january 2009 www.aosmd.com page 8 of 14 aoz8005 from figure 13 we are able to get the best result from using all of the equation above. with the value of z 1 = 80 ? , z 0 = 61 ? , c (tvs) = 0.94, = 180 and from table 1. the x(mils) equates to 580mils to give the best compensated differential impedance on the traces for the added capacitance from the aoz8005. table 1. aoz8005 msop-10 hdmi evaluation board specification number of layers 4 copper trace thickness 1.4 mils dielectric constant r 4 overall board thickness 62 mils dielectric thickness between top and ground layer 10 mils figure 10. 100 differential impedance with aoz8007 msop-10 package on it max. 97 , min. 80 figure 12. 140 differential impedance with aoz8007 msop-10 package on it max. 102 , min. 92 figure 11. 120 differential impedance with aoz8007 msop-10 package on it max. 99 , min. 86 figure 13. 160 differential impedance with aoz8007 msop-10 package on it max. 101 , min. 95
rev. 2.3 january 2009 www.aosmd.com page 9 of 14 aoz8005 figure 14. recommend layout for msop-10 package figure 15. recommended layout for sot-23 package conclusion this application section discusses esd protection while maintaining the differential impedance of a hmdi sink device. since the tvs add capacitance we must design the board to meet the hdmi requirements. this applica- tion note is a guideline to calculate and layout the pcb. different board manufacture and process will fluctuate and will cause the final board to vary slightly. you must carefully plan out a successful high speed hdmi pcb. factor such as pcb stack up, ground bounce, crosstalk and signal reflection can interfere with a signal. the layout, trace routing, board materials and impedance calculation discussed in this application note can help you design a more effective pcb using the aoz8005 devices. table 2. aoz8005 sot-23-6 evaluation board specifications 100 differential 132 differential 580 mils 100 differential 132 differential 580 mils total distance number of layers 4 copper trace thickness 1.4 mils dielectric constant r 4 overall board thickness 62 mils dielectric thickness between top and ground layer 10 mils
rev. 2.3 january 2009 www.aosmd.com page 10 of 14 aoz8005 package dimensions, sot23-6l e1 e a a2 a1 e e1 d .010mm 0.80 0.95 0.63 2.40 b l c gauge plane seating plane 0.25mm 1 notes: 1. package body sizes exclude mold flash and gate burrs. mold flash at the non-lead sides should be less than 5 mils each. 2. dimension l is measured in gauge plane. 3. tolerance 0.100mm (4 mil) unless otherwise specified. 4. followed from jedec mo-178c & mo-193c. 6. controlling dimension is millimeter. converted inch dimensions are not necessarily exact. symbols a a1 a2 b c d e e1 e e1 l 1 dimensions in millimeters min. 0.90 0.00 0.80 0.30 0.08 2.70 2.50 1.50 0.30 0 nom. 1.10 0.40 0.13 2.90 2.80 1.60 0.95 bsc 1.90 bsc max. 1.25 0.15 1.20 0.50 0.20 3.10 3.10 1.70 0.60 8 symbols a a1 a2 b c d e e1 e e1 l 1 min. 0.035 0.00 0.031 0.012 0.003 0.106 0.098 0.059 0.012 0 nom. 0.043 0.016 0.005 0.114 0.110 0.063 0.037 bsc 0.075 bsc max. 0.049 0.006 0.047 0.020 0.008 0.122 0.122 0.067 0.024 8 dimensions in inches unit: mm recommended land pattern
rev. 2.3 january 2009 www.aosmd.com page 11 of 14 aoz8005 tape and reel dimensions, sot23-6l package sot-23 (8mm) a0 b0 k0 e e1 e2 d0 d1 p0 p1 p2 t 3.15 0.10 0.10 3.20 0.10 0.10 1.40 min. 1.00 1.50 8.00 0.10 1.75 0.05 3.50 0.10 4.00 0.10 4.00 0.05 2.00 0.05 0.25 unit: mm unit: mm tape reel leader/trailer and orientation 0.30 trailer tape (300mm min., 75 empty pockets) components tape orientation in pocket leader tape (500mm min., 125 empty pockets) k0 b0 a0 d0 p0 feeding direction p2 e2 e1 e p1 d1 t w1 g v r m n w h k s tape size 8mm reel size ?180 m ?180.00 0.50 n ?60.50 w 9.00 0.30 w1 11.40 1.00 h ?13.00 +0.50 / -0.20 k 10.60 s 2.00 0.50 g ?9.00 r 5.00 v 18.00
rev. 2.3 january 2009 www.aosmd.com page 12 of 14 aoz8005 package dimensions, msop-10l l c d e a a2 a1 e b 12 (4x) e1 0.25 0.30 0.76 4.37 0.50 gauge plane seating plane unit: mm notes: 1. all dimensions are in millimeters. 2. tolerance 0.10mm unless otherwise specified. 3. package body sizes exclude mold flash and gate burrs. mold flash at the non-lead sides should be less than 5 mils each. 4. dimension l is measured in gauge plane. 5. controlling dimension is millimeter, converted inch dimensions are not necessarily exact. symbols a a1 a2 b c d e e1 e l y dimensions in millimeters min. 0.81 0.05 0.76 0.15 0.13 2.90 4.70 2.90 0.40 0 nom. 1.02 0.86 0.20 0.15 3.00 4.90 3.00 0.50 0.53 max. 1.12 0.15 0.97 0.30 0.23 3.10 5.10 3.10 0.66 0.10 6 dimensions in inches symbols a a1 a2 b c d e e1 e l y min. 0.032 0.002 0.030 0.006 0.005 0.114 0.185 0.114 0.016 0 nom. 0.040 0.034 0.008 0.006 0.118 0.193 0.118 0.0197 0.021 max. 0.044 0.006 0.038 0.012 0.009 0.122 0.201 0.122 0.026 0.004 6 recommended land pattern
rev. 2.3 january 2009 www.aosmd.com page 13 of 14 aoz8005 tape and reel dimensions, msop-10 carrier tape reel tape size 12mm reel size ?330 m ?330 0.5 t 0.30 0.05 package msop-10 (12mm) b0 3.4 0.1 a0 5.3 0.1 k0 1.4 0.1 d0 1.6 0.1 e 12.0 0.3 e1 1.75 0.10 e2 5.50 0.05 p0 8.00 0.10 p1 4.00 0.05 n ?97.0 1.0 unit: mm g m w1 s k h n w v r trailer tape 300mm min. or 75 empty sockets components tape orientation in pocket leader tape 500mm min. or 125 empty sockets t p1 d1 p2 b0 p0 d0 e2 e1 e a0 k0 w 13.00 w1 17.40 h ?13.0 +0.5/-0.2 k 10.60 s 2.0 0.5 g r v leader/trailer and orientation unit: mm section y-y' d1 1.5 +0.1/-0 p2 2.00 0.05 feeding direction
rev. 2.3 january 2009 www.aosmd.com page 14 of 14 aoz8005 park marking acow lt week & year code assembly lot code part number code aoz8005ci (sot-23) option & assembly location code 8005 io76 p11 part number code product name extension character option code AOZ8005FI (msop-10) week code year code assembly lot code assembly location code acow lt week & year code assembly lot code aoz8005cil (sot-23) option & assembly location code part number code underline denotes green code as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. this datasheet contains preliminary data; supplementary data may be published at a later date. alpha & omega semiconductor reserves the right to make changes at any time without notice. life support policy alpha & omega semiconductor products ar e not authorized for use as critical components in life support devices or systems.

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